DM506: Computer Architecture (5 ECTS)
STADS: 15000601
Level
Bachelor course
Teaching period
The course is offered in the autumn semester.
First quarter.
Teacher responsible
Email: kornerup@imada.sdu.dk
Timetable
Group |
Type |
Day |
Time |
Classroom |
Weeks |
Comment |
Common |
I |
Monday |
12-14 |
U49C |
35-41 |
|
Common |
I |
Tuesday |
10-12 |
U49C |
35-38 |
|
S1 |
TE |
Tuesday |
10-12 |
U49C |
39-41 |
|
S1 |
TE |
Thursday |
14-16 |
U26 |
40 |
|
S1 |
TE |
Friday |
12-14 |
U49C |
35-39, 41 |
|
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Comment:
Ubegrænset deltagerantal
Prerequisites:
None
Academic preconditions:
The contents of Intr. to Computer Science (DM501), Programming A and B (DM502 and DM503) must be known.
Course introductionTo introduce the student to the architecture of general purpose computers, from the logic level over the microprogram level to the conventional ISA level. Also major components in the storage hierarchy, bus architectures and the organization of pipelined CPU's.
QualificationsThe student will obtain insight into the organization of modern computers and their CPU's, so as to be able to compare and evaluate their performance on a level independent of technology. More specifically:
- to understand basic logic diagrams, and to express the functionality of basic CPU components in terms of such. Specifically to be able to express recursive definitions to minimize longest paths.
- to express the functionality of an ISA level instruction by interpretation on an underlying (micro)architecture.
- to be able to interpret ordinary binary integer and floating point number representations, and to be able to convert between these.
- to know and be able to explain the properties and limitations of the different storage components, including their addressing, and to evaluate the performance of a multi-level storage hierarchy.
- to be able to explain and discuss the exploitation of parallelism in the form of pipelining, the limitations of such, and the distribution of tasks on multiple functional units.
- to be able to explain and discuss the internal organization and internal communication paths at a high level, including communication with external units and interrupts from these.
- to express the functionality of a given algorithm as an assembler program, including to bring such a program to execution on a specific machine.
Expected learning outcomeSubject overviewThe digital logic level and microprogram level including pipelining, cache memories and other performance improving facilities. The ISA level instruction types, -formats and addressing methods, datatypes and number representations, assembler programming and virtual memories.
LiteratureMeddeles ved kursets start.
Website
This course uses
e-learn (blackboard).
Prerequisites for participating in the exam
None
Assessment and marking:
a) A 4 hour written exam where books, notes and calculators may be used. Grades according to the 7-point marking scale. External examiner. Examination only when the course had been taught. Examination in opposition terms only after acceptance from the study board.
b) Two mandatory projects that count 1 ECTS at the 5 ECTS course total. Pass/not pass, internal examiner. The projects must be passed to in order to be admitted to the exam.
Reexamination after 2. quarter.
Expected working hours
The teaching method is based on three phase model.
Forelæsninger (21 timer), eksaminatorier (21 timer) og projektarbejde.
Educational activities
Language
This course is taught in Danish.
Course enrollment
See deadline of enrolment.
Tuition fees for single courses
See fees for single courses.