DM548: Computer architecture and system programming (10 ECTS)

STADS: 15015001

Level
Bachelor course

Teaching period
The course is offered in the autumn semester.

Teacher responsible
Email: roettger@imada.sdu.dk

Timetable
Group Type Day Time Classroom Weeks Comment
Common I Monday 14-16 U174 48
Common I Monday 14-16 U166 49
Common I Tuesday 14-16 U46 36,41,44
Common I Tuesday 14-16 U167 37
Common I Tuesday 14-16 U20 39
Common I Tuesday 14-16 U48A 45
Common I Wednesday 14-16 U55 43
Common I Thursday 14-16 U133 36
Common I Thursday 14-16 U31 37
Common I Thursday 14-16 U20 38,41
Common I Thursday 14-16 U46 39-40
Common I Thursday 10-12 U23 44
Common I Thursday 10-12 U170 45
Common I Thursday 10-12 U9 47
Common I Thursday 12-14 U48A 48
Common I Thursday 12-14 U170 49
Common I Friday 12-14 U21 35
H1 TE Tuesday 14-16 U82 38
H1 TE Tuesday 14-16 U20 40
H1 TE Tuesday 14-16 U133 49
H1 TE Wednesday 14-16 U142 36
H1 TE Wednesday 14-16 U51 40
H1 TE Wednesday 14-16 U31 45,48
H1 TL Thursday 10-12 IMADA ComputerLab 37-41,48-49
H1 TE Thursday 14-16 U25A 43
H1 TE Thursday 14-16 U170 49
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Comment:
Ubegrænset deltagerantal.

Prerequisites:
None.

Academic preconditions:
The content of DM536 Introduction to Programming should be known.

The course cannot be followed if you have passed DM544 Computer Architecture, or if you have DM544 mandatory in your curriculum.



Course introduction
The course introduces the student to the architecture of general purpose computers, from the logic level over the microprogramming level to the conventional ISA level; also major components in the storage hierarchy, bus architectures and the organization of pipelined CPU's are presented. In addition, the main aspects of a system programming language are introduced.

The course builds on DM550, DM519, and DM507 and gives a professional basis for DM510 and DM546.

In relation to the learning outcomes of the degree the course has explicit focus on:

  • knowledge of principles for the construction of computer hardware and operating systems, including distributed and parallel systems
  • to understand basic logic diagrams, and to express the functionality of basic CPU components in terms of such diagrams.
  • to express the functionality of an ISA level instruction by interpretation on an underlying (micro)architecture.
  • to be able to interpret ordinary binary integer and floating point number representations, and to be able to convert between these.
  • to know and be able to explain the properties and limitations of the different storage components, including their addressing, and to evaluate the performance of a multi-level storage hierarchy.
  • to be able to explain and discuss the exploitation of parallelism in the form of pipelining, their limitations, and the distribution of tasks on multiple functional units.
  • to be able to explain and discuss the internal organization and internal communication paths at a high level, including communication with external units and interrupts from these.
  • to express the functionality of a given algorithm as an assembler program, including to bring such a program to execution on a specific machine.
  • to express the functionality of a given algorithm as a system program, including to bring such a program to execution on a specific machine.


Expected learning outcome
The learning objectives of the course are that the student demonstrates the ability to:
  • interpret elementary logic diagrams and truth tables, as well as demonstrating the functionality of the basic CPU components in form of such diagrams and tables, especially to take advantage of recursive definitions to minimize the longest path.
  • express the functionality of an ISA level instruction in the interpretation of an underlying (micro) machine architecture.
  • interpret ordinary binary integer and floating point representations, and to convert between these.
  • explain the characteristics and limitations of the different storage components, including the addressing structure, and assess the performance of a multi-level storage hierarchy.
  • explain and discuss modern CPUs internal use of parallelism in the form of pipelining, restricting use and distribution of tasks on multiple functional units.
  • explain and discuss the internal organization and internal communication paths at a high level, including communication with external devices as well as interruptions from these.
  • to express the functionality of a given algorithm as an assembler program, including to bring such a program to execution on a specific machine.
  • to express the functionality of a given algorithm as a system program, including to bring such a program to execution on a specific machine.
Subject overview
The following main topics are contained in the course:
  • The digital logic level and microprogramming level, including pipelining, cache memories and other performance improving features.
  • The ISA level instruction types, formats and addressing methods, data types and number representations, assembler programming and virtual memories.
  • A system programming language, including: variables and operators, functions, pointers, recursion, I/O, and basic data structures.
Literature
    Meddeles ved kursets start.


Website
This course uses e-learn (blackboard).

Prerequisites for participating in the exam
Two mandatory projects. The projects must be passed in order to take the written exam. Pass/fail, internal marking by teacher (15015012)

Assessment and marking:
  1. Written exam. Evaluated by external censorship by the Danish 7-mark scale. Allowed exam aids: Books and notes. 10 ECTS (15015002)
Expected working hours
The teaching method is based on three phase model.
Intro phase: 42 hours
Skills training phase: 14 hours, hereof:
 - Tutorials: 14 hours
 - Laboratory exercises: 14 hours

Educational activities Study phase: 32 hours
Educational form
Activities during the study phase:
  • Using the acquired knowledge in projects.


Language
This course is taught in English.

Course enrollment
See deadline of enrolment.

Tuition fees for single courses
See fees for single courses.